PCIe 5.0 Thread

[SteelCrysis]

https://www.tomshardware.com/news/pcie-4...38460.html

Today PCI-SIG, the organization that defines PCIe standards, announced that it ratified Version 0.9 of the PCI Express 5.0 specification, signaling that end devices will come to market in the near future.
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Unfortunately, the PCIe 4.0 standard was late compared to PCI-SIG's normal two-year cadence: PCIe 3.0 landed in 2010, leaving a 7-year gap between it and the introduction of PCIe 4.0. Given the faster arrival of the PCIe 4.0 standard, it's easy to assume it could be short-lived, especially given that vendors have already begun to design devices with new PCIe 5.0 PHY's. (Companies design end devices as early as the 0.4 revision and often launch with 0.9.)

PCI-SIG expects the two standards to co-exist in the market for some time, with PCIe 5.0 used primarily for high-performance devices that crave the ultimate in throughput, like GPUs for AI workloads, and networking applications. That means that many of the leading PCIe 5.0 devices will land in data center, networking, and HPC environments, while less-intense applications, like desktop PCs, are fine with the PCIe 4.0 interface.
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The PCI-SIG defines the specification, but it has no control over when the end devices make it to market. The PCI-SIG expects to ratify the final 1.0 revision in the first quarter of 2019, and the first PCIe 5.0 devices should debut this year. Broader availability should come in 2020.

[SteelCrysis]

https://www.tomshardware.com/news/pcie-5...9001-china

According to a report by Chinese media IThome, Jiangsu Huacun Electronic Technology has demoed its PCIe 5.0 controller at the 2019 Nantong New Generation Information Technology Expo. The memory and storage manufacturer is optimistic that the controller will be in mass-production by the end of 2020.
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Little is known about the HC9001 PCIe 5.0 controller. It's reportedly produced with the 12nm manufacturing process by the China National Research Institute and Jiangsu Huacun Electronic Technology. The HC9001, which is China's first domestic PCIe 5.0 controller, is gaining a lot of buzz, so perhaps we'll get more information as time progresses.
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An unconfirmed Intel roadmap shows the chipmaker adopting the PCIe 5.0 standard with its forthcoming Sapphire Rapids enterprise-grade processors in 2021. So far, we haven't heard anything about PCIe 5.0 on the AMD front.

[SteelCrysis]

https://www.techpowerup.com/266316/amd-t...-with-ddr5

AMD "Zen 4" will see a transition to a new silicon fabrication process, likely TSMC 5 nm-class. It will be an inflection point for the company from an I/O standpoint, as it sees the introduction of DDR5 memory support across enterprise and desktop platforms, LPDDR5 on the mobile platform, and PCI-Express gen 5.0 across the board. Besides a generational bandwidth doubling, PCIe gen 5.0 is expected to introduce several industry-standard features that help with hyper-scalability in the enterprise segment, benefiting compute clusters with multiple scalar processors, such as AMD's CDNA2. Intel introduced many of these features with its proprietary CXL interconnect.

[SteelCrysis]

https://www.techpowerup.com/278136/micro...0-switches

Applications such as data analytics, autonomous-driving and medical diagnostics are driving extraordinary demands for machine learning and hyperscale compute infrastructure. To meet these demands, Microchip Technology Inc. today announced the world's first PCI Express (PCIe) 5.0 switch solutions—the Switchtec PFX PCIe 5.0 family—doubling the interconnect performance for dense compute, high speed networking and NVM Express (NVMe ) storage. Together with the XpressConnect retimers, Microchip is the industry's only supplier of both PCIe Gen 5 switches and PCIe Gen 5 retimer products, delivering a complete portfolio of PCIe Gen 5 infrastructure solutions with proven interoperability.
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The Switchtec PFX PCIe 5.0 switch family comprises high density, high reliability switches supporting 28 lanes to 100 lanes and up to 48 non-transparent bridges (NTBs). The Switchtec technology devices support high reliability capabilities, including hot-and surprise-plug as well as secure boot authentication. With PCIe 5.0 data rates of 32 GT/s, signal integrity and complex system topologies pose significant development and debug challenges. To accelerate time-to-market, the Switchtec PFX PCIe 5.0 switch provides a comprehensive suite of debug and diagnostic features including sophisticated internal PCIe analyzers supporting Transaction Layer Packet (TLP) generation and analysis and on-chip non-obtrusive SerDes eye capture capabilities. Rapid system bring-up and debug is further supported with ChipLink—an intuitive graphical user interface (GUI) based device configuration and topology viewer that provides full access to the PFX PCIe switch's registers, counters, diagnostics and forensic capture capabilities.
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The Switchtec PFX PCIe 5.0 family of switches are sampling now to qualified customers. For additional information, contact a Microchip sales representative.

[SteelCrysis]

https://www.techpowerup.com/278239/silic...-next-year

The PCIe 5.0 protocol offers 32 GT/s per lane, making up to 64 GB/s in the full x16 implementation. However, when it comes to SSDs, as they use x4 lanes, it will increase the maximum speed of 16 GB/s, doubling the previous bandwidth. Silicon Motion, the maker of NAND flash controllers, has announced that the company is going to debut a PCIe 5.0 controller next year. "We are excited about enterprise-grade PCIe Gen5 controller, which we will have taped out early next year and sample in the second half of 2022", said Wallace Kuo, chief executive of Silicon Motion, during a conference call. Launching just in time to pair with Intel's Sapphire Rapids Xeon processors that support the PCIe 5.0 protocol, Silicon Motion is probably expecting to grab its market share there.