04-13-2018, 01:46 AM
https://www.techpowerup.com/243235/chall...rocess-ttm
Quote:Expectations may well be on their way to a bearish correction in estimates, as new research - and actual silicon production - has come to put to question previously estimated timelines for 7 nm and 5 nm products. The issue with 7 nm is a lighter one - yields aren't where manufacturers want to be as of yet. But that's expected (even if they're worse than expected) and there's still time to improve yields until actual product launches (such as AMD's Zen 2, for example). However, at 5 nm, things are getting too small for current process technology - defects and yields are way below expected levels, with various different anomalies cropping up in test production. And just consider the economics of actually finding the defects: researchers are being quoted as taking days to scan 7 nm and 5 nm-class chips for defects.
...
There's just another slight quibble with the whole new EUV production process, though: the base physics behind it. The fact remains that researchers and engineers still don't understand exactly what interactions are relevant, and occurring, in the etching of these so extremely fine patterns with EUV lighting. You'd expect some unforeseen problems arising, then, and the need for further study, trial and error, and iteration, just to understand those interactions that end up affecting final wafer quality. There goes the 2020 window, it seems.