PCIe 5.0 Thread

[SteelCrysis]

https://www.tomshardware.com/news/pcie-4...38460.html

Today PCI-SIG, the organization that defines PCIe standards, announced that it ratified Version 0.9 of the PCI Express 5.0 specification, signaling that end devices will come to market in the near future.
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Unfortunately, the PCIe 4.0 standard was late compared to PCI-SIG's normal two-year cadence: PCIe 3.0 landed in 2010, leaving a 7-year gap between it and the introduction of PCIe 4.0. Given the faster arrival of the PCIe 4.0 standard, it's easy to assume it could be short-lived, especially given that vendors have already begun to design devices with new PCIe 5.0 PHY's. (Companies design end devices as early as the 0.4 revision and often launch with 0.9.)

PCI-SIG expects the two standards to co-exist in the market for some time, with PCIe 5.0 used primarily for high-performance devices that crave the ultimate in throughput, like GPUs for AI workloads, and networking applications. That means that many of the leading PCIe 5.0 devices will land in data center, networking, and HPC environments, while less-intense applications, like desktop PCs, are fine with the PCIe 4.0 interface.
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The PCI-SIG defines the specification, but it has no control over when the end devices make it to market. The PCI-SIG expects to ratify the final 1.0 revision in the first quarter of 2019, and the first PCIe 5.0 devices should debut this year. Broader availability should come in 2020.