12-31-2020, 08:29 AM
https://www.tomshardware.com/news/intel-...d-coreboot
Quote:Alder Lake won't just be the first to bring an x86 hybrid architecture to desktops; the processors have also been pegged to leverage the high-velocity PCIe 5.0 interface. Coreboot (via Komachi_Ensaka), an open-source substitute for UEFI, seems to contain valuable information on the potential PCIe configuration that we could see on Alder Lake.
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Alder Lake-P appears to provide a flexible PCIe layout. The processor reportedly offers one PCIe 5.0 x8 lane or two PCIe 4.0 x4 lanes. It would appear that neither interface supports bifurcation, meaning you can't split up the PCIe 5.0 lane or get the PCIe 4.0 lanes to operate at x8. Nonetheless, both are backward compatible with previous-gen devices.
A single PCIe 5.0 x8 lane might sound lackluster at first, but it actually provides plenty of bandwidth. PCIe 5.0 x8 is essentially equivalent to PCIe 4.0 x16; therefore, the interface is good for up to 32 GBps of bandwidth, which is more than any consumer PCIe-based device can consume.
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There are quite a few mainstream PCIe 4.0 products, including graphics cards and M.2 SSDs, on the market right now. Tests have shown that even the fastest graphics cards have yet to saturate a PCIe 3.0 x16 interface, much less PCIe 4.0. M.2 SSDs, on the other hand, have been able to exploit the extra bandwidth that PCIe 4.0 brings to the table. We expect the PCIe 5.0 situation to play out the same.