[EDIT]hmmm.....whats going on at AMD? (and history of 3Dfx Rampage)

[BoFox]

Polaris will be released in the middle of this year, Zen will be released later this year: http://www.tomshardware.com/news/amd-zen...31338.html

If Zen surpasses my 4790K by a decent margin, I'd do an AMD build for my next box.

Same with Polaris, I'm a buyer if it beats Pascal.

This is AMDs last stand is my guess.

I'd love to go with Zen if it beats Haswell, and is cheaper than what Intel could very much do with Skylake's enhanced L4 cache by rolling out a part with 128MB eDRAM:

We have more reasons to be excited over the eDRAM in Skylake than what we saw before in Haswell with the i7-4950HQ on mobile and Broadwell on desktop with the i7-5775C, i5-5765C and the relevant Xeons. With the older platforms, the eDRAM was not a proper bidirectional cache per se.  It was used as a victim cache, such that data that was spurned from the L3 cache on the CPU ended up in eDRAM, but the CPU could not place data from the DRAM into the eDRAM without using it first (prefetch prediction). This also meant that the eDRAM was invisible to any other devices on the system, and without specific hooks couldn’t be used by most software or peripherals.

http://www.anandtech.com/show/9990/skyla...-with-gt4e

With Skylake, this changes, the eDRAM lies beyond the L3 and the System Agent as a pathway to DRAM, meaning that any data that wants DRAM space will go through the eDRAM in search for it. Rather than acting as a pseudo-L4 cache, the eDRAM becomes a DRAM buffer and automatically transparent to any software (CPU or IGP) that requires DRAM access. As a result, other hardware that communicates through the system agent (such as PCIe devices or data from the chipset) and requires information in DRAM does not need to navigate through the L3 cache on the processor.  Technically graphics workloads still need to circle around the system agent, perhaps drawing a little more power, but GPU drivers need not worry about the size of the eDRAM when it becomes buffer-esque and is accessed before the memory controller is adjusted into a higher power read request. The underlying message is that the eDRAM is now observed by all DRAM accesses, allowing it to be fully coherent and no need for it to be flushed to maintain that coherence. Also, for display engine tasks, it can bypass the L3 when required in a standard DRAM access scenario. While the purpose of the eDRAM is to be as seamless as possible, Intel is allowing some level on control at the driver level allowing textures larger than the L3 to reside only in eDRAM in order to prevent overwriting the data contained in the L3 and having to recache it for other workloads.

Any benchmarks so far on the Skylake Xeon with Iris Pro?  I'm gonna try to find some..



As to Polaris vs Pascal..  I think I'll just go with Pascal, even if Polaris is 10% faster and 10% cheaper.  I just like Nvidia better these days (PhysX, Gsync, better driver support for almost everything, etc..).