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GloFo 7nm Thread
Quote:While a move from 14 nm to 7 nm was expected to provide, at the very best, a halving in the actual size of a chip manufactured in 7 nm compared to 14 nm, Gary Patton is now saying that the are should actually be reduced by up to 2.7 times the original size. To put that into perspective, AMD's 1000 series processors on the Zeppelin die and 14 nm process, which come in at 213 mm² for the full, 8-core design, could be brought down to just 80 mm² instead. AMD could potentially use up that extra die space to either build in some overprovisioning, should the process still be in its infancy and yields need a small boost; or cram it with double the amount of cores and other architectural improvements, and still have chips that are smaller than the original Zen dies.

According to Patton, these die space saving improvements aren't the only thing that has gone on better than they expected on the 7 nm manufacturing process. Patton said that he expects this design to be able to scale pretty well to some 5 GHz operating frequencies. Now, this is the least interesting part of the 7 nm equation, even though it might not seem like it. The ability to scale up to 5 GHz frequencies will of course depend on the architecture's design being able to achieve that operating frequency stably, most of all. And of course, we've already had an historical example of an architecture that aims to go as high as possible in the frequency department with Intel's NetBurst - and we all remember how that went.
Quote:Expectations may well be on their way to a bearish correction in estimates, as new research - and actual silicon production - has come to put to question previously estimated timelines for 7 nm and 5 nm products. The issue with 7 nm is a lighter one - yields aren't where manufacturers want to be as of yet. But that's expected (even if they're worse than expected) and there's still time to improve yields until actual product launches (such as AMD's Zen 2, for example). However, at 5 nm, things are getting too small for current process technology - defects and yields are way below expected levels, with various different anomalies cropping up in test production. And just consider the economics of actually finding the defects: researchers are being quoted as taking days to scan 7 nm and 5 nm-class chips for defects.
There's just another slight quibble with the whole new EUV production process, though: the base physics behind it. The fact remains that researchers and engineers still don't understand exactly what interactions are relevant, and occurring, in the etching of these so extremely fine patterns with EUV lighting. You'd expect some unforeseen problems arising, then, and the need for further study, trial and error, and iteration, just to understand those interactions that end up affecting final wafer quality. There goes the 2020 window, it seems.

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