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Accelerators Are Going To Hit The Wall
Quote:What the team found was sobering. Performance gains in specialized silicon are fundamentally linked to the number of transistors available per millimeter of silicon over the long term, as well as the improvements to those transistors introduced with each new process node. Worse, there are fundamental limits to how much performance we can extract from improved accelerator design without simultaneous CMOS scaling improvements.

The phrase “over the long term” is important. Wentzlaff and Fuchs’ research shows that it’s not unusual for workload performance to improve dramatically when accelerators are initially deployed. Over time, as methods for optimally accelerating a given workload are explored and best practices are established, researchers converge on the most optimal approaches possible. The problems that tend to respond well to accelerators are those that are well-defined, parallelizable (think GPU workloads), and exist within a mature, well-studied domain. But this also means that the same traits that make a problem amenable to acceleration also limit the total advantage gained in the long term from doing so. The team dubs this the “accelerator wall.”

The HPC market may have had a sense of this for quite some time. Back in 2013, we wrote a story about the difficult road to exascale for mainstream supercomputers. Even back then, the TOP500 was predicting that accelerators would deliver a one-time leap in performance rankings, but not an improved rate of performance improvement.
The implications of this work are significant. It predicts domain-specific architectures will not continue to deliver significant improvements in performance once Moore’s law scaling has broken down. Even if chip designers are able to focus more tightly on improving performance in fixed transistor budgets, such gains are intrinsically limited by diminishing marginal returns for well-understood problems.

Wentzlaff and Fuch’s work points to a need for a fundamentally new approach to computing. Intel’s Meso architecture is one potential alternative. Fuchs and Wentzlaff have also suggested the use of non-CMOS materials and other types of beyond-CMOS specialization, including exploring the use of non-volatile emerging memory storage arrays as a type of workload accelerator. You can read more about the team’s effort in that domain here.

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