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TSMC 3nm Thread
#1
https://www.techpowerup.com/260464/tsmc-...nstruction
Quote:According to the sources over at DigiTimes, TSMC has acquired as much as 30 hectares of land in the Southern Taiwan Science Park to begin the construction of its fabs that are supposed to start high-volume manufacturing 3 nm node in 2023. Construction of 3 nm manufacturing facilities are set to begin in 2020 when TSMC will lay the groundwork for the new fab. The 3 nm semiconductor node is expected to be TSMC's third attempt at EUV lithography, right after the 7 nm+, and 5 nm nodes which are also based on EUV technology.
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#2
https://www.tomshardware.com/news/tsmc-t...ent-center
Quote:TSMC plans to add 8000 jobs for a new R&D center that is expected to be completed in late 2020. It will be geared towards research and development for 3nm and beyond process technology.

That was announced on Thursday by Mark Liu, executive chairman of TSMC, who said TSMC will hire an additional 8000 employees for the center. The new R&D center will be located in northern Taiwan. Construction is scheduled to start early next year and is anticipated to be completed by the end of the year. According to Taiwan News, an employee said it would be dedicated to 3nm development.
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#3
https://www.techpowerup.com/265991/tsmc-...millimeter
Quote:Imagine being able to shrink a Pentium 4 processor die to the size of a pin-head (if you can figure out how to place 478 bumps on it). TSMC revealed that its future 3 nanometer silicon fabrication node has a development target of 250 million transistors per mm². Called N3, the next-generation silicon fabrication node succeeds TSMC's N5 family of 5 nm-class nodes (that's N5 and any possible refinements).

TSMC CEO CC Wei confirmed that development of the 3 nm node is on-track, with risk production scheduled for 2021 and volume production commencing in the second half of 2022. Perhaps the most startling revelation is that TSMC has decided to stick with FinFETs for N3 owing to the maturity of the technology. Experts are of the opinion that sub-5 nm nodes will require major innovations with materials and structures. TSMC claims that N3 will provide a 10-15% speed improvement at iso-power or 25-30% power reduction at iso-speed, compared to N5.
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#4
https://www.tomshardware.com/news/tsmc-5...technology
Quote:The company also said its 3nm N3 node would begin risk production in 2021 and hit high volume manufacturing (HVM) in the second half of 2022. This node offers full node scaling over N5 and will bring up to a 10-15% performance improvement or 25-30% power reduction paired with an (up to) 1.7X density improvement. The node continues to use the FinFET architecture and offers a 1.2X increase in SRAM density and a 1.1X increase in analog density.
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#5
https://www.techpowerup.com/276087/tsmc-...ss-in-2023
Quote:The possibility barely exists to account for all the silicon manufacturing processes currently in development; TSMC themselves are rolling out 5 nm, 4 nm, 3 nm, and 2 nm processes at various points in time in the future. Now, the company has announced that it will be rolling out a revision of the 3 nm manufacturing process, named 3 nm Plus, come 2023. According to DigiTimes, the Taiwanese manufacturer's first client for this process will be Apple.

There is no information on what exactly 3 nm Plus leverages and offers over the "vanilla" 3 nm process. It could be anything from higher transistor density, lower power consumption, or higher operating frequency - or maybe a mixture of the three. The original 3 nm manufacturing process is set to offer a 15% performance gain over the current top-of-the-line 5 nm node, with 30% decreased power use and up to 70% density increase. Interestingly, TSMC is keeping their FinFet manufacturing technology, on grounds of better implementation costs and higher power efficiency compared to the more exotic GAA (Gate-All-Around) technology that its rival Samsung, for one, aims to implement in 3 nm.
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#6
https://www.techpowerup.com/279289/tsmc-...in-arizona
Quote:Taiwan Semiconductor Manufacturing Company (TSMC), one of the largest manufacturers of silicon, is seemingly making plans to build as many as six of its US-based fabs in Arizona. According to the unconfirmed report coming from UDN, TSMC could be building its Arizona-based factories for much larger capacities. Based on TSMC's classifications, the MegaFab-class of factories is the one with 25,000 WSPM output. According to the report, TSMC plans to build six additional facilities in the area where the Arizona fab is, and have a GigaFab-class (even larger type) factory present on US soil. Currently, the company operates six GigaFabs and all of them are based in Taiwan.

The GigaFab class factory is supposed to have over 100,000 WSPM output, and by building one in the US, TSMC could get much closer to big customers like Apple, NVIDIA, and AMD. Reports are saying that TSMC's primary target is 3 nm node production on 12-inch (300 mm) wafers. All six of the supposed facilities are expected to output more than 100,000 wafers at their peak, making it one of the largest projects TSMC has ever done. The Arizona location is supposed to serve as a "mega fab" facility and it is supposed to start manufacturing silicon in 2024. This information is, of course, just a rumor so you should take it with a grain of salt, as this type of information is usually only known by top-level management.
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