{"id":13818,"date":"2009-12-08T15:31:55","date_gmt":"2009-12-08T15:31:55","guid":{"rendered":"http:\/\/alienbabeltech.com\/main\/?p=13818"},"modified":"2009-12-08T15:44:55","modified_gmt":"2009-12-08T15:44:55","slug":"nvidias-chen-calls-for-zero-via-defects","status":"publish","type":"post","link":"https:\/\/alienbabeltech.com\/main\/nvidias-chen-calls-for-zero-via-defects\/","title":{"rendered":"NVIDIA’s Chen Calls for Zero Via Defects"},"content":{"rendered":"

NVIDIA needs zero defects from its foundry partners, particularly in the vias on its leading-edge graphics processors, said John Chen, vice president of technology and foundry operations at the GPU powerhouse. With 3.2 billion transistors on its 40 nm graphics processor now coming on the market, the 7.2 billion vias have become a source of problems that the industry must learn to deal with, Chen said in a keynote speech at IEDM<\/a>.<\/h4>\n

As you may know, NVIDIA\u2019s upcoming Fermi GPU has over 3 billion transistors and they are looking to their own future with even more massive GPUs. The entire speech is fascinating and we found this particularly interesting because we predicted it in September, 2008<\/a>:<\/h4>\n

“Over the next two technology generations we will get to 10 billion transistors easily,” Chen said in a speech to ~1200 IEDM participants Monday. “We need leakage to be almost zero, or at least to have leakage be undetectable.”<\/p>\n

Nvidia also needs through-silicon vias (TSVs) so that it can connect its logic transistors to DRAMs on a separate die. With 3-D interconnects, it can vertically connect two much smaller die. Graphics performance depends in part on the bandwidth for uploading from a buffer to a DRAM. “If we could put the DRAM on top of the GPU, that would be wonderful,”<\/strong> Chen said. “Instead of by-32 or by-64 bandwidth, we could increase the bandwidth to more than a thousand and load the buffer in one shot.\u201d<\/p><\/blockquote>\n

From our own blog<\/a>, 15 months ago:<\/p>\n

We know that IBM has been researching ways of stacking multiple dies on top of each other for a long time now. This (currently) has a heat disadvantage, but offers many other advantages, including but not limited to \u2013 shorter wiring with much higher speeds possible as a result. Nvidia recently joined the SOI Consortium \u2013 and this is important since SOI is a major technique employed with die stacking.
\nAnyway putting all this together, and we can see that the Tesla GPU die size is large enough now for die stacking the GPU + vRAM to be feasible for nvidia with future chips!!<\/p><\/blockquote>\n

The future we predicted is here!<\/p>\n

Mark Poppin<\/p>\n

ABT Senior Editor<\/p>\n

Please join us in our Forums<\/a><\/p>\n

Become a Fan on Facebook<\/a><\/p>\n

Follow us on Twitter<\/a><\/p>\n

For the latest updates from ABT, please join our RSS News Feed<\/a><\/p>\n

Join our Distributed Computing teams<\/p>\n