05-02-2018, 02:10 AM
https://techreport.com/review/33579/inte...production
Quote:Although Intel has said in the past that it was using self-aligned quad patterning as part of 10-nm production, Krzanich offered the eyebrow-raising prospect that the company has to employ as many as five or six multi-patterning steps to create certain 10-nm features in response to one analyst question.
Krzanich didn't say whether those figures were merely examples of multi-patterning in general or specific examples of steps needed to produce Intel 10-nm chips, but the sheer number of steps inolved in multi-patterning on that scale could be a major factor in the yield problems that Intel is experiencing. As GlobalFoundries put it to me during our foundry tour earlier this year, every interaction a silicon wafer has with lithography tools increases the chance of a defect, and multi-patterning involves a lot of interactions with those tools as a wafer is shepherded to completion.