06-30-2018, 02:57 AM
https://www.techpowerup.com/245598/intel...-nm-report
Quote:Its summary mentions quite a few juicy details of the 10 nm process. The biggest of these is the achievement of a 2.7-times increase in transistor density over the current 14 nm node, enabling Intel to cram up to 100.8 million transistors per square millimeter. A 127 mm² die with nothing but a sea of transistors, could have 12.8 billion transistors. Intel 10 nm node also utilizes third-generation FinFET technology, with a reduction in minimum gate pitch from 70 nm to 54 nm; and minimum metal pitch from 52 nm to 36 nm. 10 nm also sees Intel introduce metallization of cobalt in the bulk and anchor layers of the silicon substrate. Cobalt emerged as a good alternative to tungsten and copper as a contact material between layers, due to its lower resistance at smaller sizes,